The present invention relates generally to semiconductor processing and, more particularly, to low topography device formation prior to contact etching.
In the manufacture of semiconductor devices such as MOSFETS, making reliable electrical contact thereto is one of the more difficult processes. Such sub-micron devices are typically fabricated and isolated within a single-crystal substrate, and are further insulated by techniques such as shallow trench isolation (STI), dielectric deposition, or by growing an oxide layer on the top surface of the substrate. Once fabricated, these individual devices are then interconnected to form integrated circuits. Accordingly, electrical connections are made by etching holes or vias through the insulating layer and then by depositing high conductivity, thin-film metal structures within the vias, which metal structures are intended to make contact with the underlying devices.
However, given the topography or height differential between various device regions, it becomes difficult to accurately control the depth of the etching process. For example, when a dielectric layer (or stack) is deposited atop a formed polysilicon gate, the dielectric is then usually planarized such as by chemical mechanical polishing (CMP). Then, contact openings are patterned by photolithography techniques for etching thereafter. Because the top of the polygate is raised above the source and drain regions, the etching depth from the top of the dielectric to the top of the polygate is less than the etching depth from the top of the dielectric to the source and drain regions.
As a result, an increased device topography narrows the timing window for the etching process. If the etching is stopped prematurely, the openings over the source and drain regions may not be completely formed, thereby causing xe2x80x9copensxe2x80x9d in the device. On the other hand, if the etching duration is too long, there may be an overetching of the polygate opening. This, in turn, may cause damage to the gate itself. In either case, the result is adverse since there is a reduction in overall device yield.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for forming a planarized field effect transistor (FET). In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.
In a preferred embodiment, the active semiconductor region is formed by forming an insulating layer upon the substrate, which substrate comprises a single crystalline material. Then, a pair of window openings is formed within the insulating layer and an epitaxial layer is grown over the insulating layer and the pair of window openings, wherein the pair of mesa regions are formed over the pair of window openings. Preferably, the substrate further comprises single crystalline silicon, while the epitaxial layer comprises single crystalline silicon where it is grown over the pair of window openings.